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lm3743 n-channel fet synchronous buck controller for low output voltages general description the lm3743 is a voltage mode pwm buck controller which implements synchronous rectification. it provides a low cost, fault tolerant, and efficient point of load solution. to reduce component count several parameters are fixed, such as switching frequency and the short circuit protection level. for example the lm3743 has an operating switching frequency of 300 khz or 1 mhz and a fixed 500 mv high side current limit for switch node short-circuit protection. lm3743 is a very fault tolerant ic with switch node short-circuit, output undervoltage protection, and the ability to self recover after the removal of the fault. it avoids the need to over design components due to thermal runaway during a fault condition, thus resulting in a lower cost solution. it employs a propri- etary monotonic glitch free pre-bias start-up method suited for fpgas and asic logic devices. a 0.8v internal reference with 1.75% accuracy is ideal for sub-volt conversion. an external programmable soft-start allows for tracking and tim- ing flexibility. the driver features 1.6 ? of pull-up resistance and 1 ? of pull-down drive resistance for high power density and very efficient power processing. features n input voltage from 3.0v to 5.5v n output voltage adjustable down to 0.8v n reference accuracy: 1.75%, over full temperature and input voltage range n low-side sensing programmable current limit n fixed high-side sensing for supplemental short-circuit protection n undervoltage protection n hiccup mode protection eliminates thermal runaway during fault conditions n externally programmable soft-start with tracking capability n switching frequency options of 1 mhz or 300 khz n pre-bias start-up capability n msop-10 package applications n asic/fpga/dsp core power n broadband communications n multi-media set top boxes n networking equipment n printers/scanners n servers n low voltage distributed power typical application 20177401 september 2006 lm3743 n-channel fet synchronous buck controller for low output voltages ? 2006 national semiconductor corporation ds201774 www.national.com
connection diagram 20177402 10-lead plastic msop ns package number mub10a top view ordering information order number frequency option top mark nsc package drawing supplied as lm3743mm-300 300 khz skpb mub10a 1000 units in tape and reel lm3743mmx-300 300 khz skpb mub10a 3500 units in tape and reel LM3743MM-1000 1 mhz sknb mub10a 1000 units in tape and reel lm3743mmx-1000 1 mhz sknb mub10a 3500 units in tape and reel pin descriptions vcc (pin 1) supply rail for the controller section of the ic. a minimum capacitance of 1 f, preferably a multi-layer ce- ramic capacitor type (mlcc), must be connected as close as possible to the v cc andgndpinanda1to 4.99 ? resistance must be connected in series from the supply rail to the vcc pin. see vcc filtering in the design consid- eration section for further details. lgate (pin 2) gate drive for the low-side n-channel mos- fet. this signal is interlocked with hgate to avoid a shoot- through problem. gnd (pin 3) power ground (pgnd) and signal ground (sgnd). connect the bottom feedback resistor between this pin and the feedback pin. ilim (pin 4) low side current limit threshold setting pin. this pin sources a fixed 50 a current. a resistor of appropriate value should be connected between this pin and the drain of the low-side n-fet. fb (pin 5) feedback pin. this is the inverting input of the error amplifier used for sensing the output voltage and com- pensating the control loop. comp/en (pin 6) output of the error amplifier and enable pin. the voltage level on this pin is compared with an inter- nally generated ramp signal to determine the duty cycle. this pin is necessary for compensating the control loop. forcing this pin to ground will shut down the ic. ss/track (pin 7) soft-start and tracking pin. this pin is connected to the non-inverting input of the error amplifier during initial soft-start, or any time the voltage is below the reference. to track the rising ramp of another power supply?s output, connect a resistor divider from the output of that supply to this pin as described in application information. sw (pin 8) switch pin. the lower rail of the high-side n-fet driver. also used for the high side current limit sensing. hgate (pin 9) gate drive for the high-side n-channel mos- fet. this signal is interlocked with lgate to avoid a shoot- through problem. boot (pin 10) supply rail for the n-channel mosfet high gate drive. the voltage should be at least one gate threshold above the regulator input voltage to properly turn on the high-side n-fet. see mosfet gate drivers in the applica- tion information section for more details on how to select mosfets. lm3743 www.national.com 2
absolute maximum ratings (note 1) if military/aerospace specified devices are required, please contact the national semiconductor sales office/ distributors for availability and specifications. v cc -0.3v to 6v sw to gnd -0.3v to 6v boot to gnd -0.3v to 12v boot to sw -0.3v to 6v ss/track, ilim, comp/en,fb to gnd -0.3v to v cc junction temperature 150?c storage temperature ?65?c to 150?c soldering information lead temperature (soldering, 10sec) 260?c infrared or convection (20sec) 235?c esd rating (note 3) + / ? 2 kv operating ratings supply voltage range, v cc (note 2) 3.0v to 5.5v junction temperature range (t j ) ?40?c to +125?c electrical characteristics v cc = 3.3v, comp/en floating unless otherwise indicated in the conditions col- umn. limits in standard type are for t j = 25?c only; limits in boldface type apply over the junction temperature (t j ) range of -40?c to +125?c. minimum and maximum limits are guaranteed through test, design, or statistical correlation. typical values represent the most likely parametric norm at t j = 25?c, and are provided for reference purposes only. symbol parameter conditions min typ max units system parameters v fb fb pin voltage in regulation 3.0v v cc 5.5v 0.786 0.8 0.814 v v uvlo uvlo thresholds input voltage rising 2.84 3.0 v input voltage falling 2.45 2.66 i vcc operating v cc current f sw = 300 khz, lm3743-300 1.5 2.5 ma operating v cc current f sw = 1 mhz, lm3743-1000 1.8 3.0 ma shutdown v cc current comp/en = 0v 6 50 a i ss/track ss/track pin source current v ss/track =0v 8 10.2 12.5 a i ilim ilim pin source current v ilim =0v 42.5 50 57.5 a v ilim current limit trip level ?25 0 25 mv i comp/en comp/en pin pull-up current v comp/en =0v 4 a v hs-clim high-side current limit threshold measured at v cc pin with respect to sw 500 mv error amplifer gbw error amplifier unity gain bandwidth 30 mhz g error amplifier dc gain 90 db sr error amplifier slew rate 6 v/ms i fb fb pin bias current 10 200 na i eao eao pin sourcing/sinking current capability v comp/en = 1.5, v fb = 0.75v 1.7 ma v comp/en = 1.5, v fb = 0.85v -1 gate drive i shdn-boot boot pin shutdown current v boot -v sw = 3.3v, v comp/en =0v 25 50 a r hg-up high side mosfet driver pull-up on resistance v boot -v sw = 3.3v, i hgate = 350ma (sourcing) 1.6 ? r hg-dn high side mosfet driver pull-down on resistance v boot -v sw = 3.3v, i hgate = 350ma (sinking) 1 ? r lg-up low side mosfet driver pull-up on resistance v cc = 3.3v, i lgate = 350ma (sourcing) 1.6 ? r lg-dn low side mosfet driver pull-down on resistance v cc = 3.3v, i lgate = 350ma (sinking) 1 ? oscillator f sw oscillator frequency 3.0v v cc 5.5v, lm3743-300 255 300 345 khz 3.0v v cc 5.5v, lm3743-1000 850 1000 1150 d max max duty cycle f sw = 300 khz, lm3743-300 85 91 % f sw = 1 mhz, lm3743-1000 69 76 lm3743 www.national.com 3
electrical characteristics v cc = 3.3v, comp/en floating unless otherwise indicated in the conditions column. limits in standard type are for t j = 25?c only; limits in boldface type apply over the junction temperature (t j ) range of -40?c to +125?c. minimum and maximum limits are guaranteed through test, design, or statistical correlation. typical values represent the most likely parametric norm at t j = 25?c, and are provided for reference purposes only. (continued) symbol parameter conditions min typ max units v ramp pwm ramp amplitude 1.0 v logic inputs and outputs v comp/en-hi comp/en pin logic high trip-point 0.65 0.9 v v comp/en-lo comp/en pin logic low trip-point 0.1 0.45 v hiccup mode n lscycles low-side sensing cycles before hiccup mode 15 cycles n lsreset low-side sensing cycles reset without activating current limit 32 cycles v uvp under voltage protection comparator threshold 400 mv t glich-uvp under voltage protection fault time before hiccup mode 7s t hiccup hiccup timeout 5.5 ms t ss soft-start time coming out of hiccup mode 3.6 ms thermal resistance ja junction to ambient thermal resistance 235 ?c/w note 1: absolute maximum ratings indicate limits beyond which damage to the device may occur. operating ratings indicate conditions for which the device operates correctly. operating ratings do not imply guaranteed performance limits. note 2: practical lower limit of v cc depends on selection of the external mosfet. see the mosfet gate drivers section under application information for further details. note 3: esd using the human body model which is a 100 pf capacitor discharged through a 1.5 k ? resistor into each pin. test method is per jesd22?a114. lm3743 www.national.com 4
block diagram 20177403 lm3743 www.national.com 5
typical performance characteristics v in = 3.3, t j = 25?c, i load = 1a unless otherwise specified. d max vs temperature f sw = 1 mhz d max vs temperature f sw = 300 khz 20177455 20177456 fb vs temperature f sw = 1 mhz fb vs temperature f sw = 300 khz 20177457 20177458 frequency vs temperature f sw = 1 mhz frequency vs temperature f sw = 300 khz 20177459 201774a2 lm3743 www.national.com 6
typical performance characteristics v in = 3.3, t j = 25?c, i load = 1a unless otherwise specified. (continued) frequency vs v cc f sw = 1 mhz frequency vs v cc f sw = 300 khz 20177461 20177462 i shdn_boot vs temperature f sw = 1 mhz i shdn_boot vs temperature f sw = 300 khz 20177463 20177464 i lim vs temperature f sw = 1 mhz i lim vs temperature f sw = 300 khz 20177465 20177466 lm3743 www.national.com 7
typical performance characteristics v in = 3.3, t j = 25?c, i load = 1a unless otherwise specified. (continued) i vcc vs temperature f sw = 1 mhz i vcc vs temperature f sw = 300 khz 20177467 20177468 line regulation v out = 1.2v, i out = 1a, f sw = 300 khz line regulation v out = 1.5v, i out = 1a, f sw = 1 mhz 20177469 20177470 load regulation v in = 3.3v, f sw = 1 mhz load regulation v in = 3.3v, f sw = 300 khz 20177471 20177472 lm3743 www.national.com 8
typical performance characteristics v in = 3.3, t j = 25?c, i load = 1a unless otherwise specified. (continued) efficiency vs load f sw = 1 mhz, v out = 2.5v efficiency vs load f sw = 1 mhz, v out = 1.8v 20177489 20177488 efficiency vs load f sw = 1 mhz, v out = 1.5v efficiency vs load f sw = 1 mhz, v out = 1.2v 20177487 20177474 efficiency vs load f sw = 1 mhz, v out = 1.0v efficiency vs load f sw = 1 mhz, v out = 0.8v 20177473 20177490 lm3743 www.national.com 9
typical performance characteristics v in = 3.3, t j = 25?c, i load = 1a unless otherwise specified. (continued) efficiency vs load f sw = 300 khz, v out = 2.5v efficiency vs load f sw = 300 khz, v out = 1.8v 20177495 20177494 efficiency vs load f sw = 300 khz, v out = 1.5v efficiency vs load f sw = 300 khz, v out = 1.2v 20177493 20177492 efficiency vs load f sw = 300 khz, v out = 1.0v efficiency vs load f sw = 300 khz, v out = 0.8v 20177491 20177496 lm3743 www.national.com 10
typical performance characteristics v in = 3.3, t j = 25?c, i load = 1a unless otherwise specified. (continued) load transient response f sw = 1 mhz, v in = 3.3v, i load = 100 ma to 3.5a (refer to an-1450 for bom) load transient response f sw = 300 khz, v in = 3.3v, i load = 100 ma to 3.5a (refer to an-1450 for bom) 20177497 20177498 shutdown r load =1 ? ,v in = 5v pre bias startup 20177499 201774a0 lm3743 www.national.com 11
application information theory of operation the lm3743 is a voltage mode pwm buck controller featur- ing synchronous rectification at 300 khz or 1 mhz. in steady state operation the lm3743 is always synchronous even at no load, thus simplifying the compensation design. the lm3743 ensures a smooth and controlled start-up to support pre-biased outputs. two levels of current limit protection enhance the robustness of the power supply and requires no current sense resistor in the power path. the primary level of protection is the low side current limit and is achieved by sensing the voltage v ds across the low side mosfet. the second level of protection is the high side current limit, which protects power components from extremely high currents, caused by switch node short to ground. normal operation while in normal operation, the lm3743 ic controls the output voltage by controlling the duty cycle of the power fets. the dc level of the output voltage is determined by a pair of feedback resistors using the following equation: (designators refer to the typical application circuit in the front page) for synchronous buck regulators, the duty ratio d is approxi- mately equal to: start up the lm3743 ic begins to operate when the comp/en pin is released from a clamped condition and the voltage at the v cc pin has exceeded 2.84v. once these two conditions have been met the internal 10a current source begins to charge the soft-start capacitor connected at the ss/track pin. during soft-start the voltage on the soft-start capacitor is connected internally to the non-inverting input of the error amplifier. the soft-start period lasts until the voltage on the soft-start capacitor exceeds the lm3743 reference voltage of 0.8v. at this point the reference voltage takes over at the non-inverting error amplifier input. the capacitance deter- mines the length of the soft-start period, and can be approxi- mated by: c4=(t ss x 10 a) / 0.8v where t ss is the desired soft-start time. in the event of either v cc falling below uvlo or comp/en pin being pulled below 0.45v, the soft-start pin will discharge c4 to allow the output voltage to recover smoothly. start up with pre-bias a pre-bias output is a condition in which current from another source has charged up the output capacitor of the switching regulator before it has been turned on. the lm3743 features a proprietary glitch free monotonic pre-bias start-up method designed to ramp the output voltage from a pre-biased rail to the target nominal output voltage. the ic limits the on time of the low-side fet to 150 ns (typ) during soft-start, while allowing the high-side fet to adjust it?s time according to soft-start voltage, v out , and the internal voltage ramp. any further commutation of the load current is carried by the body diode of the low-side fet or an external schottky diode, if used. the low side current limit is active during soft-start while allowing the asynchronous switching. when soft-start is completed, the on-time of the low-side fet is allowed to increase in a controlled fashion up to the steady state duty cycle determined by the control loop. a plot of the lm3743 starting up into a pre-biased condition is shown in the typical performance characteristics section. note that the pre-bias voltage must not be greater than the target output voltage of the lm3743, otherwise the lm3743 will pull the pre-bias supply down during steady state opera- tion. tracking with equal soft-start time the lm3743 can track the output of a master power supply during soft-start by connecting a resistor divider to the ss/ track pin. in this way, the output voltage slew rate of the lm3743 will be controlled by the master supply for loads that require precise sequencing. when the tracking function is used, no soft-start capacitor should be connected to the ss/track pin. however in all other cases, a capacitor value (c4) of at least 560 pf should be connected between the soft-start pin and ground. one way to use the tracking feature is to design the tracking resistor divider so that the master supply?s output voltage (v out1 ) and the lm3743?s output voltage (represented sym- bolically in figure 1 as v out2 , i.e. without explicitly showing the power components) both rise together and reach their target values at the same time. for this case, the equation governing the values of the tracking divider resistors r t1 and r t2 is: the top resistance r t2 must be set to 1 k ? in order to limit current into the lm3743 during uvlo or shutdown. the final voltage of the ss/track pin should be slightly higher than the feedback voltage of 0.8v, say about 0.85v as in the above equation. the 50 mv difference will ensure the lm3743 to reach regulation slightly before the master sup- ply. if the master supply voltage was 5v and the lm3743 20177430 figure 1. tracking circuit lm3743 www.national.com 12
application information (continued) output voltage was 1.8v, for example, then the value of r t1 needed to give the two supplies identical soft-start times would be 205 ? . a timing diagram for the equal soft-start time case is shown in figure 2 . tracking with equal slew rates the tracking feature can alternatively be used not to make both rails reach regulation at the same time but rather to have similar rise rates (in terms of output dv/dt). in this case, the tracking resistors can be determined based on the fol- lowing equation: for the example case of v out1 = 5v and v out2 = 1.8v, with r t2 set to 1 k ? as before, r t1 is calculated from the above equation to be 887 ? . a timing diagram for the case of equal slew rates is shown in figure 3 . tracking and shutdown sequencing lm3743 is designed to track the output of a master power supply during start-up, but when the master supply powers down the output capacitor of the lm3743 will discharge cycle by cycle through the low-side fet. the off-time will reach 100% when the voltage at the track pin reaches zero volts. this condition will persist as long as the master output voltage is zero volts and the drivers of the lm3743 are still on. for example if the load is required to not be discharged, the drivers must be shut-off before the master powers down. this is achieved by shutting down the lm3743 or bring v cc below uvlo falling threshold. in this case the load will not be discharged. shutdown the lm3743 ic can be put into shutdown mode by bringing the voltage at the comp/en pin below 0.45v (typ). the quiescent current during shutdown is approximately 6 a (typ). during shutdown both the high-side and low-side fets are disabled. the soft-start capacitor is discharged through an internal fet so that the output voltage rises in a con- trolled fashion when the part is enabled again. when en- able da4a pull-up current increases the charge of the compensation capacitors. under voltage lock-out (uvlo) if v cc drops below 2.66v (typ), the chip enters uvlo mode. uvlo consists of turning off the top and bottom fets and remaining in that condition until v cc rises above 2.84v (typ). as with shutdown, the soft-start capacitor is discharged through an internal fet, ensuring that the next start-up will be controlled by the soft-start circuitry. mosfet gate drive the lm3743 has two gate drivers designed for driving n-channel mosfets in synchronous mode. power for the high gate driver is supplied through the boot pin, while driving power for the low gate is provided through the v cc pin. the boot voltage is supplied from a local charge pump structure which consists of a schottky diode and 0.1 f capacitor, shown in figure 4 . since the bootstrap capacitor (c10) is connected to the sw node, the peak voltage im- pressed on the boot pin is the sum of the input voltage (v in ) plus the voltage across the bootstrap capacitor (ignor- ing any forward drop across the bootstrap diode). the boot- strap capacitor is charged up by v in (called v boot_dc here) whenever the upper mosfet turns off. 20177431 figure 2. tracking with equal soft-start time 20177433 figure 3. tracking with equal slew rate 20177434 figure 4. charge pump circuit and driver circuitry lm3743 www.national.com 13
application information (continued) the output of the low-side driver swings between v cc and ground, whereas the output of the high-side driver swings between v in +v boot_dc and v in . to keep the high-side mosfet fully on, the gate pin voltage of the mosfet must be higher than its instantaneous source pin voltage by an amount equal to the ?miller plateau?. it can be shown that this plateau is equal to the threshold voltage of the chosen mosfet plus a small amount equal to i out /g. here i out is the maximum load current of the application, and g is the transconductance of this mosfet (typically about 100 for logic-level devices). that means we must choose v boot_dc to at least exceed the miller plateau level. this may therefore affect the choice of the threshold voltage of the external mosfets, and that in turn may depend on the chosen v in rail. so far in the discussion above, the forward drop across the bootstrap diode has been ignored. but since that does affect the output of the driver, it is a good idea to include this drop in the following examples. looking at the typical application schematic, this means that the difference voltage v in -v d1 , which is the voltage the bootstrap capacitor charges up to, must always be greater than the maximum tolerance limit of the threshold voltage of the upper mosfet. here v d1 is the forward voltage drop across the bootstrap diode d1. this voltage drop may place restrictions on the type of mosfet selected. the capacitor c10 serves to maintain enough voltage be- tween the top mosfet gate and source to control the device even when the top mosfet is on and its source has risen up to the input voltage level. the charge pump circuitry is fed from v in , which can operate over a range from 3.0v to 5.5v. using this basic method the voltage applied to the high side gate v in -v d1 . this method works well when v in is 5v 10%, because the gate drives will get at least 4.0v of drive voltage during the worst case of v in-min = 4.5v and v d1-max = 0.5v. logic level mosfets generally specify their on-resistance at v gs = 4.5v. when v cc = 3.3v 10%, the gate drive at worst case could go as low as 2.5v. logic level mosfets are not guaranteed to turn on, or may have much higher on-resistance at 2.5v. sub-logic level mosfets, usu- ally specified at v gs = 2.5v, will work, but are more expen- sive and tend to have higher on-resistance. low-side current limit the main current limit of the lm3743 is realized by sensing the voltage drop across the low-side fet as the load current passes through it. the r dson of the mosfet is a known value; hence the voltage across the mosfet can be deter- mined as: v ds =i out xr dson the current flowing through the low-side mosfet while it is on is the falling portion of the inductor current. the current limit threshold is determined by an external resistor, r1, connected between the switching node and the ilim pin. a constant current (i ilim ) of 50 a typical is forced through r1, causing a fixed voltage drop. this fixed voltage is compared against v ds and if the latter is higher, the current limit of the chip has been reached. to obtain a more accurate value for r1 you must consider the operating values of r dson and i ilim at their operating temperatures in your application and the effect of slight parameter variations from part to part. r1 can be found by using the following equation using the r dson value of the low side mosfet at it?s expected hot temperature and the absolute minimum value expected over the full temperature range for the i ilim which is 42.5 a: r1=r dson-hot xi clim /i ilim for example, a conservative 15a current limit (i clim )ina 10a design with a r dson-hot of 10 m ? would require a 3.83 k ? resistor. the lm3743 enters current limit mode if the inductor current exceeds the set current limit threshold. the inductor current is first sampled 50 ns after the low-side mosfet turns on. note that in normal operation mode the high-side mosfet always turns on at the beginning of a clock cycle. in current limit mode, by contrast, the high-side mosfet on-pulse is skipped. this causes inductor current to fall. unlike a normal operation switching cycle, however, in a current limit mode switching cycle the high-side mosfet will turn on as soon as inductor current has fallen to the current limit threshold. the low-side current sensing scheme can only limit the current during the converter off-time, when inductor current is falling. therefore in a typical current limit plot the valleys are normally well defined, but the peaks are variable, ac- cording to the duty cycle, see figure 5 . the pwm error amplifier and comparator control the pulse of the high-side mosfet, even during current limit mode, meaning that peak inductor current can exceed the current limit threshold. for example, during an output short-circuit to ground, and as- suming that the output inductor does not saturate, the maxi- mum peak inductor current during current limit mode can be calculated with the following equation: where t sw is the inverse of switching frequency f sw . the 200 ns term represents the minimum off-time of the duty cycle, which ensures enough time for correct operation of the current sensing circuitry. in order to minimize the temperature effects of the peak inductor currents, the ic enters hiccup mode after 15 over current events, or a long current limit event that lasts 15 switching cycles (the counter is reset when 32 non-current 20177444 figure 5. current limit threshold lm3743 www.national.com 14
application information (continued) limit cycles occur in between two current limit events). hic- cup mode will be discussed in further detail in the ?hiccup mode and internal soft-start? section. high-side coarse current limit the lm3743 employs a comparator to monitor the voltage across the high-side mosfet when it is on. this provides protection for short circuits from switch node to ground or the case when the inductor is shorted, which the low side current limit cannot detect. a 200 ns blanking time period after the high-side fet turns on is used to prevent switching transient voltages from tripping the high-side current limit without cause. if the difference between v cc pin and sw pin voltage exceeds 500 mv, the lm3743 will immediately enter hiccup mode (see hiccup mode section). output under-voltage protection (uvp) after the end of soft-start the output uvp comparator is activated. the threshold is 50% of the feedback voltage. once the comparator indicates uvp for more than 7 s typ. (glitch filter time), the ic goes into hiccup mode. hiccup mode and internal soft-start hiccup protection mode is designed to protect the external components of the circuit (output inductor, fets, and input voltage source) from thermal stress. during hiccup mode, the lm3743 disables both the high-side and low-side fets and begins a cool down period of 5.5 ms. at the conclusion of this cool down period, the regulator performs an internal 3.6 ms soft-start. there are three distinct conditions under which the ic will enter the hiccup protection mode: 1. the low-side current sensing threshold has exceeded the current limit threshold for fifteen sampled cycles, see figure 6 . each cycle is sampled at the start of each off time (t off ). the low-side current limit counter is reset when 32 consecutive non-current limit cycles occur in between two current limit events. 2. the high-side current limit comparator has sensed a differential voltage larger than 500 mv. 3. the voltage at the fb pin has fallen below 0.4v, and the uvp comparator has sensed this condition for 7 s (during steady state operation). the band gap reference, the external soft-start, and internal hiccup soft-start of 3.6 ms (typ) connect to the non-inverting input of the error amplifier through a multiplexer. the lowest voltage of the three connects directly to the non-inverting input. hiccup mode will not discharge the external soft-start, only uvlo or shut-down will. when in hiccup mode the internal 5.5 ms timer is set, and the internal soft-start capaci- tor is discharged. after the 5.5 ms timeout, the internal 3.6 ms soft-start begins, see figure 7 . during soft-start, only low-side current limit and high side current limit can put the lm3743 into hiccup mode. for example, if the low-side current limit is 10a, then once in overload the low-side current limit controls the valley current and only allows an average amount of 10a plus the ripple current to pass through the inductor and fets for 15 switch- ing cycles. in such an amount of time, the temperature rise is very small. once in hiccup mode, the average current through the high-side fet is: i hsf-ave =(i clim + ? i) x [ d(15 cycles x t sw ) ] / 5.5 ms equals 71 ma. with an arbitrar y d = 60%, ripple current of 3a, and a 300 khz switching frequency. the average current through the low-side fet is: i lsf-ave =(i clim + ? i) x [ (1?d) x (15 cycles x t sw ) ] / 5.5 ms equals 47 ma, and the average current through the inductor is: i l-ave =(i clim + ? i) x [ (15 cycles x t sw ) ] / 5.5 ms equals 118 ma. design considerations the following is a design procedure for selecting all the components in the typical application circuit on the front page. this design converts 5v (v in ) to 1.8v (v out )ata maximum load of 10a with an efficiency of 90% and a switching frequency of 300 khz. the same procedures can 20177452 figure 6. entering hiccup mode 20177406 figure 7. hiccup time-out and internal soft-start lm3743 www.national.com 15
application information (continued) be followed to create many other designs with varying input voltages, output voltages, load currents, and switching fre- quency. switching frequency selection of the operating switching frequency is based on trade-offs between size, cost, efficiency, and response time. for example, a lower frequency will require larger more expensive inductors and capacitors. while a higher switch- ing frequency will generally reduce the size of these compo- nents, but will have a reduction in efficiency. fast switching converters allow for higher loop gain bandwidths, which in turn have the ability to respond quickly to load and line transients. for the example application we have chosen a 300 khz switching frequency because it will reduce the switching power losses and in turn allow for higher conduc- tion losses considering the same power loss criteria, thus it is possible to sustain a higher load current. output inductor the output inductor is responsible for smoothing the square wave created by the switching action and for controlling the output current ripple ( ? i out ) also called the ac component of the inductor current. the dc current into the load is equal to the average current flowing in the inductor. the induc- tance is chosen by selecting between trade-offs in efficiency, size, and response time. the recommended percentage of ac component to dc current is 30% to 40%, this will provide the best trade-off between energy requirements and size, (read an-1197 for theoretical analysis). another criteria is the ability to respond to large load transient responses; the smaller the output inductor, the more quickly the converter can respond. the equation for output inductor selection is: here we have plugged in the values for input voltage, output voltage, switching frequency, and 30% of the maximum load current. this yields an inductance of 1.34 h. the output inductor must be rated to handle the peak current (also equal to the peak switch current), which is (i out + (0.5 x ? i out )) = 11.5a, for a 10a design and a ac current of 3a. the coiltronics dr125?1r5 is 1.5 h, is rated to 13.8a rms current, and has a direct current resistance (dcr) of 3 m ? . after selecting the coiltronics dr125?1r5 for the output inductor, actual inductor current ripple must be re-calculated with the selected inductance value. this information is needed to determine the rms current through the input and output capacitors. re-arranging the equation used to select inductance yields the following: v in(max) is assumed to be 10% above the steady state input voltage, or 5.5v at v in = 5.0v. the re-calculated current ripple will then be 2.69a. this gives a peak inductor/switch current will be 11.35a. output capacitor the output capacitor in a switching regulator is selected on the basis of capacitance, equivalent series resistance (esr), size, and cost. in this example the output current is 10a and the expected type of capacitor is an aluminum electrolytic, as with the input capacitors. an important specification in switching converters is the output voltage ripple ? v out .at 300 khz the impedance of most capacitors is very small compared to esr, hence esr becomes the main selection criteria. in this design the load requires a 2% ripple , which results in a ? v out of 36 mv p-p . thus the maximum esr is then: esr max is 13 m ? . aluminum electrolytic (al-e), tantalum (ta), solid aluminum, organic, and niobium (nb) capacitors are all popular in switching converters. in general, by the time enough capacitors have been paralleled to obtain the desired esr, the bulk capacitance is more than enough to supply the load current during a transient from no-load to full load. the number and type of capacitors used depends mainly on their size and cost. one exception to this is multi-layer ceramic capacitors. mlccs have very low esr, but also low capacitance in comparison with other types. this makes them attractive for lower power designs. for higher power or for fast load transients the number of ml- ccs needed often increases the size and cost to unaccept- able levels. because the load could transition quickly from 0 to 10a, more bulk capacitance is needed than the mlccs can provide. one compromise is a solid electrolytic pos- cap from sanyo or sp-caps from panasonic. poscap and spcaps often have large capacitances needed to supply currents for load transients, and low esrs. the 6tpd470m by sanyo has 470 f, and a maximum esr of 10 m ? . solid electrolytics have stable esr relative to temperature, and capacitance change is relatively immune to bias voltage. tantalums (ta), niobium (nb), and al-e are good solutions for ambient operating temperatures above 0?c, however their esr tends to increase quickly below 0?c ambient op- erating temperature, so these capacitor types are not rec- ommended for this area of operation. input capacitor the input capacitors in a buck converter are subjected to high rms current stress. input capacitors are selected for their ability to withstand the heat generated by the rms current and the esr as specified by the manufacturer. input rms ripple current is approximately: lm3743 www.national.com 16
application information (continued) where duty cycl ed=v out /v in . the worst-case ripple for a buck converter occurs during full load and when the duty cycle (d) is 0.5. when multiple capacitors of the same type and value are paralleled, the power dissipated by each input capacitor is: where n is the number of paralleled capacitors, and esr is the equivalent series resistance of each capacitor. the equa- tion above indicates that power loss in each capacitor de- creases rapidly as the number of input capacitors increases. for this 5v to 1.8v design the duty cycle is 0.36. for a 10a maximum load the rms current is 4.8a. connect one or two 22 f mlcc as close as possible across the drain of the high-side mosfet and the source of the low-side mosfet, this will provide high frequency decou- pling and satisfy the rms stress. a bulk capacitor is recom- mended in parallel with the mlcc in order to prevent switch- ing frequency noise from reflecting back into the input line, this capacitor should be no more than 1inch away from the mlcc capacitors. mosfets selection of the power mosfets is governed by a trade-off between cost, size, and efficiency. one method is to deter- mine the maximum cost that can be endured, and then select the most efficient device that fits that price. using a spreadsheet to estimate the losses in the high-side and low-side mosfets is one way to determine relative efficien- cies between different mosfets. good correlation between the prediction and the bench result is not guaranteed. losses in the high-side mosfet can be broken down into conduction loss, gate charging loss, and switching loss. conduction, or i 2 r loss, is approximately: for the high side fet: p c =d(i out 2 xr dson-hi x 1.3) for the low side fet: p c =(1-d)x(i out 2 xr dson-lo x 1.3) in the above equations the factor 1.3 accounts for the in- crease in mosfet r dson due to heating. alternatively, the 1.3 can be ignored and the r dson of the mosfet estimated using the r dson vs. temperature curves in the mosfet manufacturer datasheet. gate charging loss results from the current driving the gate capacitance of the power mosfets, and is approximated as: p gc =(v cc )xq g xf sw v cc is the driving voltage (see mosfet gate driver sec- tion) and q g is the gate charge of the mosfet. if multiple devices will be placed in parallel, their gate charges can simply be summed to form a cumulative q g . switching loss occurs during the brief transition period as the high-side mosfet turns on and off, during which both cur- rent and voltage are present in the channel of the mosfet. it can be approximated as: p sw =0.5xv in xi out x(t r +t f )xf sw where t r and t f are the rise and fall times of the mosfet. switching loss occurs in the high-side mosfet only. for this example, the maximum drain-to-source voltage ap- plied to either mosfet is 5.5v. the maximum drive voltage at the gate of the high-side mosfet is 5.0v, and the maxi- mum drive voltage for the low-side mosfet is 5.5v. for designs between 5a and 10a, single mosfets in so-8 provide a good trade-off between size, cost, and efficiency. v cc filtering to ensure smooth dc voltage for the chip suppl ya1f (c3), x5r mlcc type or better must be placed as close as possible to the v cc and gnd pin. together with a small 1 to 4.99 ? resistor placed between the input rail and the v cc pin, a low pass filter is formed to filter out high frequency noise from injecting into the v cc rail. since v cc is also the sense pin for the high-side current limit, the resistor should connect close to the drain of the high-side mosfet to prevent ir drops due to trace resistance. a second design consider- ation is the low pass filter formed by c3 and r6 on the v cc pin, a fast slew rate, large amplitude load transient may cause a larger voltage droop on c in than on v cc pin. this may lead to a lower current at which high-side protection may occur. thus increase the bulk input capacitor if the high-side current limit is engaging due to a dynamic load transient behavior as explained above. bootstrap diode (d1) the mbr0520 and bat54 work well as a bootstrap diode in most designs. schottky diodes are the preferred choice for the bootstrap circuit because of their low forward voltage drop. for circuits that will operate at high ambient tempera- ture the schottky diode datasheet must be read carefully to ensure that the reverse current leakage at high temperature does not increase enough to deplete the charge on the bootstrap capacitor while the high side fet is on. some schottky diodes increase their reverse leakage by as much as 1000 times at high temperatures. fast rectifier and pn junction diodes maintain low reverse leakage even at high ambient temperature. these diode types have higher for- ward voltage drop but can still be used for high ambient temperature operation. control loop compensation the lm3743 uses voltage-mode (?vm?) pwm control to cor- rect changes in output voltage due to line and load tran- sients. vm requires careful small signal compensation of the control loop for achieving high bandwidth and good phase margin. the control loop is comprised of two parts. the first is the power stage, which consists of the duty cycle modulator, output inductor, output capacitor, and load. the second part is the error amplifier, which for the lm3743 is a 30 mhz op-amp used in the classic inverting configuration. figure 8 shows the regulator and control loop components. lm3743 www.national.com 17
application information (continued) one popular method for selecting the compensation compo- nents is to create bode plots of gain and phase for the power stage and error amplifier. combined, they make the overall bandwidth and phase margin of the regulator easy to see. software tools such as excel, mathcad, and matlab are useful for showing how changes in compensation or the power stage affect system gain and phase. the power stage modulator provides a dc gain a dc that is equal to the input voltage divided by the peak-to-peak value of the pwm ramp. this ramp is 1.0v pk-pk for the lm3743. the inductor and output capacitor create a double pole at frequency f dp , and the capacitor esr and capacitance cre- ate a single zero at frequency f esr . for this example, with v in = 5.0v, these quantities are: in the equation for f dp , the variable r l is the power stage resistance, and represents the inductor dcr plus the on resistance of the top power mosfet. r o is the output voltage divided by output current. the power stage transfer function g ps is given by the following equation, and figure 9 shows bode plots of the phase and gain in this example. a=lc o (r o +r c ) b=l+c o (r o r l +r o r c +r c r l ) c=r o +r l the double pole at 6 khz causes the phase to drop to approximately -140? at around 15 khz. the esr zero, at 33.9 khz, provides a +90? boost that prevents the phase from dropping to -180 o . if this loop were left uncompensated, the bandwidth would be approximately 15 khz and the phase margin 40?. in theory, the loop would be stable, but would suffer from poor dc regulation (due to the low dc gain) and would be slow to respond to load transients (due to the low bandwidth.) in practice, the loop could easily become unstable due to tolerances in the output inductor, capacitor, or changes in output current, or input voltage. therefore, the loop is compensated using the error amplifier and a few passive components. for this example, a type iii, or three-pole-two-zero approach gives optimal bandwidth and phase. in most voltage mode compensation schemes, including type iii, a single pole is placed at the origin to boost dc gain 20177413 figure 8. power stage and error amp 20177418 20177419 figure 9. power stage gain and phase lm3743 www.national.com 18
application information (continued) as high as possible. two zeroes f z1 and f z2 are placed at the double pole frequency to cancel the double pole phase lag. then, a pole, f p1 is placed at the frequency of the esr zero. a final pole f p2 is placed at one-half of the switching fre- quency. the gain of the error amplifier transfer function is selected to give the best bandwidth possible without violat- ing the nyquist stability criteria. in practice, a good crossover point is one-fifth of the switching frequency, or 60 khz for this example. the generic equation for the error amplifier transfer function is: in this equation the variable a ea is a ratio of the values of the capacitance and resistance of the compensation compo- nents, arranged as shown in figure 8 .a ea is selected to provide the desired bandwidth. a starting value of 80,000 for a ea should give a conservative bandwidth. increasing the value will increase the bandwidth, but will also decrease phase margin. designs with 45-60? are usually best because they represent a good trade-off between bandwidth and phase margin. in general, phase margin is lowest and gain highest (worst-case) for maximum input voltage and mini- mum output current. one method to select a ea is to use an iterative process beginning with these worst-case conditions. 1. increase a ea 2. check overall bandwidth and phase margin 3. change v in to minimum and recheck overall bandwidth and phase margin 4. change i o to maximum and recheck overall bandwidth and phase margin the process ends when both bandwidth and phase margin are sufficiently high. for this example input voltage can vary from 4.5v to 5.5v and output current can vary from 0 to 10a, and after a few iterations a moderate gain factor of 90 db is used. the error amplifier of the lm3743 has a unity-gain band- width of 30 mhz. in order to model the effect of this limitation, the open-loop gain can be calculated as: the new error amplifier transfer function that takes into account unity-gain bandwidth is: the gain and phase of the error amplifier are shown in figure 10 . in vm regulators, the top feedback resistor r2 forms a part of the compensation. setting r2 to 10 k ? 1%, usually gives values for the other compensation resistors and capacitors that fall within a reasonable range. (capacitances > 1pf, resistances < 1m ? ) c7, c8, c9, r4, and r5 are selected to provide the poles and zeroes at the desired frequencies, using the following equations: 20177423 20177424 figure 10. error amp. gain and phase lm3743 www.national.com 19
application information (continued) in practice, a good trade off between phase margin and bandwidth can be obtained by selecting the closest 10% capacitor values above what are suggested for c7 and c8, the closest 10% capacitor value below the suggestion for c9, and the closest 1% resistor values below the sugges- tions for r4, r5. note that if the suggested value for r5 is less than 100 ? , it should be replaced by a short circuit. following this guideline, the compensation components will be: c7=47pf 10%, c9 = 1.5 nf 10% c8 = 2.2 nf 10%, r4 = 22.6 k ? 1% r5 = 2.1 k ? 1% the transfer function of the compensation block can be derived by considering the compensation components as impedance blocks z f and z i around an inverting op-amp: as with the generic equation, g ea-actual must be modified to take into account the limited bandwidth of the error ampli- fier. the result is: the total control loop transfer function h is equal to the power stage transfer function multiplied by the error amplifier transfer function. h=g ps xh ea the bandwidth and phase margin can be read graphically from bode plots of h ea as shown in figure 11 . the bandwidth of this example circuit is 59 khz, with a phase margin of 60?. efficiency calculations the following is a sample calculation. a reasonable estimation of the efficiency of a switching buck controller can be obtained by adding together the output power (p out ) loss and the total power loss (p loss ): 20177429 20177450 figure 11. overall loop gain and phase lm3743 www.national.com 20
application information (continued) the output power (p out ) for the typical application circuit design is (1.8v x 10a) = 18w. the total power (p loss ), with an efficiency calculation to complement the design, is shown below. the majority of the power losses are due to the low side and high side mosfet?s losses. the losses in any mosfet are switching (p sw ), conduction losses (p cnd ), and gate charg- ing losses (p gate ) fet switching loss (p sw ) p sw =p sw(on) +p sw(off) p sw =0.5xv in xi out x(t r +t f )xf sw p sw =0.5x5vx10ax300khzx67ns p sw = 503 mw the si4866dy has a typical turn-on rise time t r and turn-off fall time t f of 32 ns and 35 ns, respectively. the switching losses for the upper fet (q1) is 0.503w. the low side fet (q2) does not incur switching losses. fet conduction loss (p cnd ) p cnd =p cnd1 +p cnd2 p cnd1 =i 2 out xr ds(on) xkxd p cnd2 =i 2 out xr ds(on) x k x (1-d) r ds(on) = 4.5 m ? and the k factor accounts for the increase in r ds(on) due to heating . k = 1.3 at t j = 100?c p cnd1 = (10a) 2 x 4.5 m ? x 1.3 x 0.36 p cnd2 = (10a) 2 x 4.5 m ? x 1.3 x (1 - 0.36) p cnd =p cnd1 +p cnd2 p cnd = 211 mw + 374 mw = 585 mw fet gate charging loss (p gate ) p gate_h =nx(v cc -v d1 )xq gs xf sw p gate_l =nxv cc xq gs xf sw p gates =[1x( 5.0v-0.4v)x22ncx300khz]+[1x (5.0v)x22ncx300khz] p gates =29mw+33mw=62mw the value n is the total number of fets used and q gs is the typical gate-source charge value, which is 21 nc. for the si4866dy the gate charging loss is 62 mw. thus the total mosfet losses are: p fet =p sw +p cnd +p gates = 503 mw + 585 mw + 62 mw p fet = 1.15 w there are few additional losses that are taken into account: ic loss (p ic ) p op =i q_vcc xv cc p dr =[[(nxq gs xf sw )/d]+[(nxq gs xf sw ) / (1?d) ]] xv cc where p op is the operating loss, p dr is the driver loss, i q-vcc is the typical operating v cc current p op = ( 1.3 ma x 5.0v ) p dr =[(1x22ncx300khz)/.36]+[(1x22ncx300 khz)/.64]xv cc p ic =p op +p dr p ic = 6.5 mw + 137 mw = 143.5 mw input capacitor loss (p cap ) where, here n is the number of paralleled capacitors, esr is the equivalent series resistance of each, and p cap is the dissi- pation in each. so for example if we use only one input capacitor of 10m ? . p cap = 230 mw output inductor loss (p ind ) p ind =i 2 out x dcr where dcr is the dc resistance. therefore, for example p ind = (10a) 2 x3m ? p ind = 302 mw total system efficiency p loss =p fet +p ic +p cap +p ind pcb layout considerations to produce an optimal power solution with the lm3743, good layout and design of the pcb are as important as component selection. the following are several guidelines to aid in creating a good layout. for an extensive pcb layout expla- nation refer to an-1229. separate power ground and signal ground good layout techniques include a dedicated ground plane, preferably on an internal layer. signal level components like the compensation and feedback resistors should be con- nected to a section of this internal plane, signal ground. the signal ground section of the plane should be connected to the power ground at a single point. the best place to connect the signal ground and power ground is right at the gnd pin of the ic. low impedance power path the power path includes the input capacitors, power fets, output inductor, and output capacitors. keep these compo- nents on the same side of the pcb and connect them with thick traces or copper planes on the same layer. vias add resistance and inductance to the power path, and have high impedance connections to internal planes than do top or bottom layers of a pcb. if heavy switching currents must be routed through vias and/or internal planes, use multiple vias in parallel to reduce their resistance and inductance. the lm3743 www.national.com 21
application information (continued) power components must be kept close together. the longer the paths that connect them, the more they act as antennas, radiating unwanted emi. minimize the switch node copper the plane that connects the power fets and output inductor together radiates more emi as it gets larger. use just enough copper to give low impedance to the switching currents. kelvin traces for sense lines the drain and the source of the high-side fet should be connected as close as possible to the v cc filter resistor (r6) and the sw pin and each pin should connect with a separate trace. the feedback trace should connect the positive node of the output capacitor and connect to the top feedback resistor (r2). keep this trace away from the switch node and from the output inductor. if driving the comp pin low with a signal bjt or mosfet make sure to keep the signal tran- sistor as close as possible to the pin and keep the trace away from emi radiating nodes and components. lm3743 www.national.com 22
physical dimensions inches (millimeters) unless otherwise noted msop-10 pin package ns package number mub10a national does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and national reserves the right at any time without notice to change said circuitry and specifications. for the most current product information visit us at www.national.com. life support policy national?s products are not authorized for use as critical components in life support devices or systems without the express written approval of the president and general counsel of national semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. banned substance compliance national semiconductor follows the provisions of the product stewardship guide for customers (csp-9-111c2) and banned substances and materials of interest specification (csp-9-111s2) for regulatory environmental compliance. details may be found at: www.national.com/quality/green. lead free products are rohs compliant. national semiconductor americas customer support center email: new.feedback@nsc.com tel: 1-800-272-9959 national semiconductor europe customer support center fax: +49 (0) 180-530 85 86 email: europe.support@nsc.com deutsch tel: +49 (0) 69 9508 6208 english tel: +44 (0) 870 24 0 2171 fran?ais tel: +33 (0) 1 41 91 8790 national semiconductor asia pacific customer support center email: ap.support@nsc.com national semiconductor japan customer support center fax: 81-3-5639-7507 email: jpn.feedback@nsc.com tel: 81-3-5639-7560 www.national.com lm3743 n-channel fet synchronous buck controller for low output voltages

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